The reduction in DRAM memory cell refresh times at high integration densities is frequently caused by, among other things, parasitic short-channel induced charge leakage from the cell's storage capacitor. To address this reduction, attempts have been made to implant plug ions into the cell's contact regions to reduce leakage currents. A method according to one such attempt is illustrated by FIGS. 1-6. In particular, FIG. 1 illustrates a semiconductor substrate 11 having a cell array region and a peripheral circuit region. The cell array region is defined by a field oxide isolation region 12. This conventional method includes the steps of forming a blanket gate oxide film (not shown) on a face of the substrate 11. A conductive layer and insulating layer are then deposited and patterned to form insulated electrodes 14 having insulating caps 15 thereon. Next, lightly doped N-type regions 17 are formed by implanting N-type dopants into the substrate 11.
Referring now to FIG. 2, a blanket insulating film 19 is then deposited on the substrate 11. Then, a photoresist layer PR1 is patterned and used as an etching mask to form contact holes 21 in the blanket insulating film 19. A plug ion implanting step is then performed to reduce leakage currents from subsequently formed electrodes of storage capacitors, by recovering the damage generating in the semiconductor substrate 11 when the contact holes 21 were formed. Based on the plug ion implanting step, second impurity regions 23 are formed. Referring now to FIG. 3, the layer of photoresist PR1 is removed and then a layer of polysilicon is deposited in the contact holes 21 and patterned to form storage electrodes 25. Using conventional techniques, a dielectric film 27 and plate electrode 29 are then formed in sequence to complete the formation of storage capacitors.
As illustrated best by FIG. 4, a second layer of photoresist is patterned to expose a portion of the peripheral circuit region where NMOS transistors are to be formed. A selective etching step is then performed to convert the exposed insulating film 19 to sidewall spacers 31 and then a self-aligned high dose implantation step is performed to form N-type source and drain regions 33. Similarly, as illustrated by FIG. 5, a third layer of photoresist is patterned to expose a portion of the peripheral circuit region where PMOS transistors are to be formed. A selective etching step is then performed to convert the exposed insulating film 19 to sidewall spacers 35. A self-aligned high dose implantation step is then performed to form P-type source and drain regions 37.
Finally, as illustrated best by FIG. 6, the third layer of photoresist is removed and then a blanket insulating film 39 is deposited. A planarization step is then performed using another insulating film 41 such as borophosphosilicate glass (BPSG). A layer of photoresist (not shown) is then patterned and used as an etching mask to form a bit line contact hole. A layer of undoped polysilicon is then deposited into the bit line contact hole and patterned to form a bit line 43. Thereafter, plug ions are implanted to reduce the contact resistance between the bit line 43 and the cell active area, and thereby form a bit line contact region 45.
Notwithstanding the above described method of forming DRAM memory cells which includes steps of forming storage electrode contact regions and bit line contact regions in sequence, there continues to be a need for improved methods of forming integrated circuit memory devices containing memory cells therein.